The differential impedance for HDMI to MIPI DSI interfaces is 100 ohms, and this is non-negotiable for both standards when you're dealing with high-speed signal lines. HDMI specifies a differential impedance of 100 ohms ±15% for its TMDS (Transition Minimized Differential Signaling) pairs, while MIPI DSI (Display Serial Interface) requires 100 ohms ±10% for its differential data lanes. These numbers come straight from the HDMI 1.4/2.0 specifications and the MIPI Alliance D-PHY specification v1.2 or v2.0. In practice, if you're designing a conversion board or an adapter that bridges HDMI to MIPI DSI, you must maintain that 100-ohm differential impedance across the entire signal path, from the HDMI connector through the bridge chip (like the LT8918 or TC358870) and out to the MIPI DSI connector. Failing to hit this target causes signal reflections, increased jitter, and bit errors that can lead to flickering displays, no image, or even permanent damage to the driver ICs. Let's break down the specifics, the design challenges, and the real-world data you need to get this right.
The core impedance requirement: why 100 ohms?
Both HDMI and MIPI DSI use differential signaling, which means each data bit is transmitted as a voltage difference between two wires (a pair). The differential impedance is the impedance that the signal sees between those two wires. For HDMI, the TMDS clock and data channels operate at speeds up to 3.4 Gbps per lane (HDMI 1.4) or 6 Gbps per lane (HDMI 2.0), and the standard mandates 100 ohms ±15% to ensure signal integrity over typical cable lengths up to 15 meters. MIPI DSI, on the other hand, uses D-PHY with data rates up to 1.5 Gbps per lane (D-PHY v1.2) or 2.5 Gbps per lane (D-PHY v2.0), and it requires 100 ohms ±10% for the differential pairs. The tighter tolerance in MIPI DSI reflects the shorter PCB traces and the need for lower jitter in mobile displays. When you're converting HDMI to MIPI DSI, the bridge chip acts as a re-driver, but the PCB traces on both sides must still match 100 ohms. If the HDMI input traces are 100 ohms but the MIPI output traces drift to 90 ohms, you'll see a 10% impedance mismatch, which causes a reflection coefficient of about 0.05 (5% of the signal is reflected). At 1.5 Gbps, this reflection can degrade the eye diagram opening by 15-20%, leading to data errors.
PCB stackup and trace geometry for 100-ohm differential impedance
To achieve 100-ohm differential impedance on a 4-layer PCB, you need to carefully control the trace width, spacing, and the dielectric material. For a typical FR4 board with a dielectric constant (Dk) of 4.2 to 4.5, a common stackup is: top layer (signal), ground plane, power plane, bottom layer (signal). For microstrip lines on the top layer, with a dielectric height (H) of 4 mils (0.1 mm) between the trace and the ground plane, a 5-mil (0.127 mm) trace width and a 5-mil (0.127 mm) spacing between the differential pair will give you roughly 100 ohms. But this is a rough estimate. Using a field solver like Polar SI9000 or a calculator from a PCB fab house, you'll get more precise numbers. For example, with H=4 mils, trace width=5.5 mils, spacing=5.5 mils, and trace thickness=1.4 mils (1 oz copper), the differential impedance calculates to 100.2 ohms. If you switch to a 6-layer board with a thinner dielectric (H=3 mils), the trace width might drop to 4.5 mils with 4.5 mils spacing. The key is to keep the impedance tolerance within ±10% (90 to 110 ohms) for MIPI DSI, and ideally within ±5% for the HDMI side to avoid signal degradation. In one real-world design for an hdmi to 4 lane mipi dsi adapter, the PCB used a 4-layer stackup with a 0.062-inch (1.6 mm) total thickness, a 0.008-inch (0.2 mm) prepreg layer between the top and ground plane, and 6-mil traces with 6-mil spacing to hit 100 ohms. The measured impedance was 98.5 ohms on the HDMI side and 99.2 ohms on the MIPI side, which is well within spec.
Signal integrity data: what happens when impedance drifts?
Let's look at some hard numbers. If you have a 100-ohm differential trace and the impedance drops to 85 ohms (a 15% mismatch), the reflection coefficient is (85-100)/(85+100) = -0.081, or about 8.1% of the signal is reflected back. At 1.5 Gbps (MIPI DSI data rate), the rise time is about 150 ps. A 10-inch (25.4 cm) trace on FR4 has a propagation delay of about 1.7 ns, so the reflection arrives back at the driver after 3.4 ns. This reflection can cause overshoot or undershoot of 200-300 mV on a 1.2V MIPI signal, which can trigger false switching in the receiver. In a test with a 100-ohm matched board versus a board with 85-ohm traces, the eye diagram at the MIPI receiver showed a vertical opening of 600 mV (p-p) for the matched board, but only 450 mV for the mismatched board. The jitter increased from 25 ps to 55 ps, which is above the 50 ps limit for D-PHY v1.2. For HDMI, the situation is worse at higher speeds. At 3.4 Gbps, a 100-ohm to 90-ohm mismatch (10% off) produces a reflection coefficient of -0.053, which can cause a 10% reduction in the eye height. In a production run of 100 adapter boards, those with impedance within ±5% had a 98% pass rate in HDMI compliance testing, while boards with ±15% deviation had a 72% pass rate. So, the impedance tolerance directly impacts yield.
Connector and cable impedance: the hidden variable
The differential impedance isn't just about PCB traces. The HDMI connector itself has a specified impedance of 100 ohms, but real-world connectors can vary. For example, a standard HDMI Type A connector from a reputable manufacturer like Molex or TE has a differential impedance of 100 ohms ±15% across the pin field. But if you use a cheap clone connector, the impedance can drop to 85 ohms or spike to 115 ohms. Similarly, the MIPI DSI connector (typically a 0.5 mm pitch FPC connector) is designed for 100 ohms, but the flex cable that connects to the display can have impedance variations. A 30-pin, 0.5 mm pitch FPC cable with a 100-ohm differential impedance specification might actually measure 95 to 105 ohms depending on the bending radius. In one test, a 10 cm FPC cable bent at a 90-degree angle showed a 5-ohm drop in differential impedance due to the change in the dielectric spacing. This is why you should always include impedance test coupons on your PCB and measure the actual impedance with a TDR (Time Domain Reflectometer) before mass production. For the hdmi to 4 lane mipi dsi adapter, the design includes a 50-ohm single-ended impedance for the control signals (I2C, reset, etc.) but the high-speed lanes are strictly 100 ohms differential.
Material selection and its impact on impedance
The dielectric constant (Dk) of the PCB material directly affects the impedance. Standard FR4 has a Dk of 4.2 to 4.5, but it varies with frequency. At 1 GHz, the Dk of FR4 is about 4.2, but at 3 GHz, it drops to 4.0. This means the impedance of your traces changes with frequency. For a 100-ohm trace designed at 1 GHz, the impedance might be 102 ohms at 3 GHz due to the lower Dk. This is a 2% shift, which is manageable. But if you use a high-loss material like CEM-3, the Dk can be 4.8 to 5.2, which would require different trace geometries. For high-speed designs, you should use a low-loss material like Rogers 4350B (Dk=3.48) or Isola FR408 (Dk=3.7). These materials have a tighter Dk tolerance (±0.05) and lower loss tangent (0.0037 vs. 0.02 for FR4). In a comparison, a 10-inch trace on FR4 at 1.5 Gbps has a loss of about 1.5 dB, while the same trace on Rogers 4350B has a loss of 0.8 dB. This extra 0.7 dB loss can reduce the eye height by 10-15%. For a cost-sensitive product like an adapter board, FR4 is usually acceptable if you keep the trace lengths under 6 inches (15 cm) and use a proper stackup. But for longer traces, you need better materials. The hdmi to 4 lane mipi dsi adapter uses a 4-layer FR4 board with a 0.062-inch thickness, and the trace lengths are kept under 4 inches to minimize loss.
Layout guidelines for 100-ohm differential pairs
When routing the HDMI to MIPI DSI signals, you must follow specific layout rules to maintain the 100-ohm impedance. First, keep the differential pair traces as short as possible, ideally under 6 inches (15 cm) for MIPI DSI lanes running at 1.5 Gbps. Second, maintain a constant spacing between the traces in the pair. If you have to route around a via or a component, use a serpentine pattern to keep the pair length matched, but avoid abrupt changes in spacing. A 10% change in spacing (e.g., from 5 mils to 5.5 mils) can cause a 2-3 ohm impedance shift. Third, avoid routing differential pairs over gaps in the ground plane. If you cut the ground plane under a trace, the impedance can increase by 10-20 ohms. In one design, a trace that crossed a split in the ground plane had a measured impedance of 118 ohms, which caused a 15% mismatch. Fourth, use ground vias adjacent to the differential pair vias to provide a return path. For a via transition, the impedance can drop by 5-10 ohms if the via is not properly stitched. In a test, a via with two ground vias placed 30 mils away had a differential impedance of 98 ohms, while a via with no ground vias had 88 ohms. So, always add ground vias within 50 mils of the signal vias. For the hdmi to 4 lane mipi dsi adapter, the layout includes ground vias every 0.5 inches along the differential pairs, and the trace lengths are matched to within 5 mils for each lane.
Bridge chip impedance considerations
The bridge chip (e.g., LT8918, TC358870, or Analogix ANX7625) has its own impedance requirements. Most of these chips have internal 50-ohm single-ended termination resistors that are used to match the 100-ohm differential impedance. For HDMI inputs, the chip typically has a 50-ohm resistor to ground on each line of the differential pair, which creates a 100-ohm differential termination. For MIPI DSI outputs, the chip uses a 100-ohm differential termination resistor between the pair. The chip's datasheet will specify the recommended PCB trace impedance, which is almost always 100 ohms differential. But the chip's package and bond wires can add inductance. For example, the LT8918 has a package inductance of about 2 nH per pin, which at 1.5 Gbps (with a rise time of 150 ps) can cause a 5-ohm impedance bump. To compensate, you might need to slightly reduce the trace impedance by 2-3 ohms on the output side. In practice, this is done by adjusting the trace width or spacing by 0.5 mils. The chip's datasheet will often include a recommended PCB layout with specific trace geometries. For the LT8918, the recommended trace width is 5 mils with 5 mils spacing on a 4-mil dielectric, which gives 100 ohms. But if you use a different stackup, you need to recalculate. The hdmi to 4 lane mipi dsi adapter uses the LT8918, and the PCB layout follows the reference design with a 4-layer board and 6-mil traces on a 4-mil prepreg, which gives 99.5 ohms measured.
Testing and verification: how to measure differential impedance
You can't just assume your PCB will hit 100 ohms. You need to measure it. The standard tool is a TDR (Time Domain Reflectometer), which sends a fast pulse down the trace and measures the reflected signal. For differential pairs, you use a differential TDR probe. The measurement should be done at the connector pins and at the chip pins. For a 100-ohm target, a good result is 98 to 102 ohms. Anything outside 90 to 110 ohms requires a redesign. In a production run of 500 boards for the hdmi to 4 lane mipi dsi adapter, the TDR measurements showed an average impedance of 99.3 ohms with a standard deviation of 2.1 ohms. The worst-case board had 95.8 ohms, which is still within the ±10% spec. But if you're using a 2-layer board (which is cheaper), the impedance control is worse. A 2-layer board with a 0.062-inch thickness and no ground plane can have a differential impedance of 120 to 150 ohms because the return path is not well defined. So, always use at least a 4-layer board for HDMI to MIPI DSI conversion. Another test is to use an eye diagram mask test. For MIPI DSI, the eye must have a minimum vertical opening of 200 mV and a horizontal opening of 0.45 UI (Unit Interval). At 1.5 Gbps, one UI is 666 ps, so the horizontal opening must be at least 300 ps. With a 100-ohm matched board, the eye opening is typically 600 mV and 450 ps. With a 90-ohm board, it drops to 450 mV and 350 ps, which is still passable but marginal. With an 85-ohm board, the eye might fail the mask test.
Real-world examples and common mistakes
I've seen designs where the engineer used a 50-ohm single-ended impedance for the MIPI DSI traces, thinking it was the same as differential. That's a common mistake. Single-ended 50 ohms is for coaxial lines, not differential pairs. If you route a 50-ohm single-ended trace for each line of a differential pair, the differential impedance will be about 100 ohms only if the traces are far apart (more than 3 times the trace width). But if they are close (which they should be for differential signaling), the coupling between them reduces the differential impedance. For example, two 50-ohm single-ended traces with a 5-mil spacing on a 4-mil dielectric will have a differential impedance of about 85 ohms. So, you must design for 100 ohms differential, not 50 ohms single-ended. Another mistake is using a via that is too large. A 20-mil via pad can add 2-3 pF of capacitance, which at 1.5 Gbps creates a 50-ohm impedance bump. Use 12-mil via pads with 8-mil holes instead. Also, avoid using 90-degree bends; use 45-degree or arc bends to reduce impedance discontinuities. In one case, a board with 90-degree bends had a 5-ohm impedance spike at each bend, which caused a 10% increase in jitter. The hdmi to 4 lane mipi dsi adapter uses 45-degree bends and 12-mil vias to keep the impedance consistent.
Power integrity and its effect on impedance
The differential impedance of the signal traces is also affected by the power distribution network (PDN). If the ground plane has high inductance or poor decoupling, the return current for the differential signal can be disrupted, causing the impedance to vary. For MIPI DSI, the power supply for the D-PHY is typically 1.2V or 1.8V, and the ripple should be less than 50 mV p-p. If the ripple is 100 mV, the signal integrity degrades, and the effective impedance of the traces can shift by 2-3 ohms due to the change in the driver's output impedance. Use at least 10 µF and 0.1 µF decoupling capacitors near the bridge chip, and place them within 0.1 inches of the power pins. The ground plane should be continuous under the entire high-speed area. In a test, a board with a 0.5-inch gap in the ground plane under the MIPI traces had a 10-ohm impedance increase and a 20% reduction in the eye opening. So, always keep the ground plane solid.
Frequency-dependent impedance and skin effect
At high frequencies, the skin effect increases the resistance of the traces, which can slightly reduce the differential impedance. At 1.5 Gbps, the skin depth in copper is about 1.7 µm, so the current flows on the